发明名称 INSTRUCTION AND LOGIC TO PROVIDE VECTOR COMPRESS AND ROTATE FUNCTIONALITY
摘要 Instructions and logic provide vector compress and rotate functionality. Some embodiments, responsive to an instruction specifying: a vector source, a mask, a vector destination and destination offset, read the mask, and copy corresponding unmasked vector elements from the vector source to adjacent sequential locations in the vector destination, starting at a vector destination offset location. In some embodiments, the unmasked vector elements from the vector source are copied to adjacent sequential element locations modulo the total number of element locations in the vector destination. In some alternative embodiments, copying stops whenever the vector destination is full, and upon copying an unmasked vector element from the vector source to an adjacent sequential element location in the vector destination, the value of a corresponding field in the mask is changed to a masked value. Alternative embodiments zero elements of the vector destination, in which no element from the vector source is copied.
申请公布号 KR20140056082(A) 申请公布日期 2014.05.09
申请号 KR20130130028 申请日期 2013.10.30
申请人 INTEL CORP. 发明人 ULIEL TAL;OULD AHMED VALL ELMOUSTAPHA;VALENTINE ROBERT
分类号 G06F9/30 主分类号 G06F9/30
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