发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE DESIGN METHOD
摘要 <p>PROBLEM TO BE SOLVED: To design a first dummy gate electrode pattern for first etching and a second dummy gate electrode pattern for second etching of a semiconductor integrated circuit device in which gate electrodes of different types are formed through two etching processes, without violation of a design manual (DM).SOLUTION: A semiconductor integrated circuit device design method comprises: a first step of defining a first dummy gate electrode pattern so as to get close to an optimum occupancy which satisfies a DM; and a second step of defining a second dummy gate electrode pattern after the first step, in which when a mask pattern for the second dummy gate electrode pattern does not satisfy occupancy in the DM, the optimum occupancy is changed within a range of the occupancy defined in the DM and the process proceeds to the first step after the second step, and when the mask pattern for the second dummy gate electrode pattern satisfies the occupancy in the DM, the first and the second dummy gate electrode patterns are determined.</p>
申请公布号 JP2014082394(A) 申请公布日期 2014.05.08
申请号 JP20120230454 申请日期 2012.10.18
申请人 RENESAS ELECTRONICS CORP 发明人 SUGIYAMA KOICHI;IKEDA YOICHI;SAO KOICHI
分类号 H01L21/82;G03F1/70;H01L21/3205;H01L21/336;H01L21/768;H01L21/822;H01L21/8247;H01L23/522;H01L27/04;H01L27/10;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L21/82
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