发明名称 |
MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATE |
摘要 |
A memory device can include a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines independently and concurrently in synchronism with at least a first clock signal; an address port configured to receive address values on consecutive, different transitions of a second clock, each address value corresponding to an access on a different one of the data ports; and a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein. |
申请公布号 |
WO2013025262(A3) |
申请公布日期 |
2014.05.08 |
申请号 |
WO2012US32645 |
申请日期 |
2012.04.06 |
申请人 |
CYPRESS SEMICONDUCTOR;MAHESHWARI, DINESH;BARBARA, BRUCE;MARINO, JOHN |
发明人 |
MAHESHWARI, DINESH;BARBARA, BRUCE;MARINO, JOHN |
分类号 |
G06F13/00 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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