发明名称 WAFER-LEVEL THROUGH SILICON VIA (TSV) MANUFACTURING METHOD
摘要 <p>A wafer-level through silicon via (TSV) manufacturing method: firstly depositing a silicon oxide insulation layer (102) on the front and back faces of a silicon wafer (101), then forming a TSV pattern on a photoresist (103) on the front and back faces, and transferring the TSV pattern onto the silicon wafer (101); conducting wet etching until a TSV (105) is formed; subsequently, conducting wet etching to remove the oxide layers on both faces of the silicon wafer; using a thermal oxidation process to re-deposit a silicon oxide insulation layer (106) on the front and back faces of the silicon wafer and the side wall of the TSV at the same time; using a magnetron sputtering process to deposit a metal layer TiW/Au (107, 108) on both faces of the silicon wafer; and then using a silicon wafer double-face electroplating process to cover the entire TSV with metal layers to realize double-face conduction. Compared with the technique for interconnecting TSVs having a dry-etched vertical side wall, the present technique has the key advantages of good reliability, high yield and the like, and greatly facilitates subsequent film deposition and electroplating deposition owing to the sloped wet-etched TSV side wall, thus being simple in operation, low in cost and suitable for industrial production.</p>
申请公布号 WO2014067288(A1) 申请公布日期 2014.05.08
申请号 WO2013CN77029 申请日期 2013.06.09
申请人 SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATIONTECHNOLOGY, CHINESE ACADEMY OF SCIENCES 发明人 CHEN, XIAO;LUO, LE;XU, GAOWEI
分类号 H01L21/768 主分类号 H01L21/768
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