发明名称 Reducing Pattern Loading Effect in Epitaxy
摘要 A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.
申请公布号 US2014127886(A1) 申请公布日期 2014.05.08
申请号 US201213671243 申请日期 2012.11.07
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY,;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 SUNG HSUEH-CHANG;KWOK TSZ-MEI;CHEN KUAN-YU;LI KUN-MU
分类号 H01L21/20 主分类号 H01L21/20
代理机构 代理人
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