| 摘要 |
A First-in First-out (FIFO) memory comprising a latch array and a RAM array, the latch array being assigned higher priority to receive data than the RAM array. Incoming data are pushed into the latch array while the latch array has vacancies. Upon the latch array becoming empty, incoming data are pushed into the RAM array during a spill-over period. The RAM array may comprise two spill regions with only one active to receive data at a spill-over period. The allocation of data among the latch array and the spill regions of the RAM array can be transparent to external logic. |
