发明名称 |
Structure and method to form a thermally stable silicide in narrow dimension gate stacks |
摘要 |
An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height. |
申请公布号 |
GB2487857(B) |
申请公布日期 |
2014.05.07 |
申请号 |
GB20120005375 |
申请日期 |
2010.09.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
AHMET S OZCAN;CHRISTIAN LAVOIE;ANTHONY G DOMENICUCCI |
分类号 |
H01L21/28;H01L29/423;H01L29/66;H01L29/78 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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