Control gate word line driver circuit for multigate memory

摘要

A memory (101) having an array (103) of multi-gate memory cells and a word line driver circuit (115) coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.