| 摘要 |
A processor and method comprises a fused multiply-add (FMA) circuit which includes a multiplier unit 110 and an adder unit 125 to compute a fused multiply add operation. If certain input data values are received at the FMA circuit, an exception occurs and components of the circuit will be clock gated to disable them and prevent them from toggling. If either of the two inputs to the multiplier unit are zero, then the multiplier and adder are gated and the addend provided as output 135. If one of the multiplier units is equal to one, then the multiplier is gated and the other multiplier input is directly provided to the adder. If the addend is zero, then the adder is gated and the product of the multiplier provided as output. If one of the multiplier inputs is equal to 2N, then the multiplier is gated and the other multiplier input directed to a left or right shifter 114. This processor might form part of multi-core processing system, and it is implemented to save power by bypassing the arithmetic units when they are not required. |
