发明名称 Power efficient processor architecture
摘要 In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
申请公布号 GB2507696(A) 申请公布日期 2014.05.07
申请号 GB20140002807 申请日期 2011.09.06
申请人 INTEL CORPORATION 发明人 ANDREW J HERDRICH;RAMESHKUMAR G ILLIKKAL;RAVISHANKAR IYER;SADOGOPAN SRINIVASAN;JAIDEEP MOSES;SRIHARI MAKINENI
分类号 G06F9/50;G06F1/32 主分类号 G06F9/50
代理机构 代理人
主权项
地址