发明名称 Prioritsing events to which a processor is to respond
摘要 A computer system comprises a processor (106) configured to respond to events from a plurality of sources, and a prioritisation module (104) implemented in hardware and configured to prioritise the events for the processor. The prioritisation module comprises one or more decision modules (108) comprising multiple, prioritised inputs (110) configured to receive respective event flags relating to events from respective sources. The decision module stores a source identifier of the source corresponding to the highest priority asserted event flag. The processor can read the stored source identifier to identify the source of an event to which the processor is to respond. In this way, the decision as to which event a processor should respond to next is offloaded from the processor and implemented in hardware in the prioritisation module. This can reduce the workload of the processor and thereby result in a more efficient computer system.
申请公布号 GB201405323(D0) 申请公布日期 2014.05.07
申请号 GB20140005323 申请日期 2014.03.25
申请人 IMAGINATION TECHNOLOGIES LIMITED 发明人
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