发明名称 Programmable logic device with a self-power down mechanism
摘要 Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.
申请公布号 US8717062(B2) 申请公布日期 2014.05.06
申请号 US201213353246 申请日期 2012.01.18
申请人 YAP CHEE WAI;ALTERA CORPORATION 发明人 YAP CHEE WAI
分类号 H03K19/177 主分类号 H03K19/177
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