发明名称 Signal wiring system and jitter suppression circuit
摘要 Reducing jitter in signal wiring without requiring a larger circuit scale is difficult in the technology of the related art. A signal wiring system to resolve the above problem therefore includes an output unit to output a differential signal, a receiver unit to receive differential signals from the output unit, a jitter suppression circuit to suppress the amount of the jitter in the differential signal received by the receiver unit according to a suppression coefficient, and a signal wiring unit for conveying a differential signal from the output unit and including a wiring length set according to a suppression coefficient in the jitter suppression circuit.
申请公布号 US8718214(B2) 申请公布日期 2014.05.06
申请号 US201213403124 申请日期 2012.02.23
申请人 AOKI YASUSHI;RENESAS ELECTRONICS CORPORATION 发明人 AOKI YASUSHI
分类号 H04L25/00 主分类号 H04L25/00
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