发明名称 Repurposing data lane as clock lane by migrating to reduced speed link operation
摘要 Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.
申请公布号 US8717882(B2) 申请公布日期 2014.05.06
申请号 US201113175798 申请日期 2011.07.01
申请人 IYER VENKATRAMAN;BLANKENSHIP ROBERT G.;BAUM ALLEN J.;INTEL CORPORATION 发明人 IYER VENKATRAMAN;BLANKENSHIP ROBERT G.;BAUM ALLEN J.
分类号 H04J3/06 主分类号 H04J3/06
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