发明名称 Scan chain diagnostic using scan stitching
摘要 An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.
申请公布号 US8719651(B1) 申请公布日期 2014.05.06
申请号 US201113330466 申请日期 2011.12.19
申请人 DEV NILABHA;CHAKRAVARTHY CHILLARIGE SAMEER;BHABU SHALEEN;CADENCE DESIGN SYSTEMS, INC. 发明人 DEV NILABHA;CHAKRAVARTHY CHILLARIGE SAMEER;BHABU SHALEEN
分类号 G01R31/28;G06F11/00 主分类号 G01R31/28
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