发明名称 |
PARALLEL PROCESSING OF MULTIPLE BLOCK COHERENCE OPERATIONS |
摘要 |
A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream. |
申请公布号 |
US2014122810(A1) |
申请公布日期 |
2014.05.01 |
申请号 |
US201213660003 |
申请日期 |
2012.10.25 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
BHORIA NAVEEN;DAMODARAN RAGURAM |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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