FLEXIBLE SCRAMBLER/DESCRAMBLER ARCHITECTURE FOR A TRANSCEIVER

摘要

An apparatus includes a polynomial register (510) having a plurality of bits, where the polynomial register is configured to store a user-defined polynomial. A transceiver (406, 408) is coupled to a first bus, a second bus, and the polynomial register. The transceiver includes a self-synchronous scrambler (502) that is configured to generate a scrambled signal from a first signal using the user-defined polynomial and a self-synchronous descrambler (506) that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.