DYNAMIC PRIORITY MANAGEMENT OF MEMORY ACCESS

摘要

A system includes multiple master devices (102 - 1 12) sharing a common memory (130), and a memory controller (124) including at least one memory refresh scheduler (126). When a master device (102 - 112) needs higher priority for memory access, the master device (102 - 112) sends a dynamic priority signal (DP1 - DP4) to the memory refresh scheduler (126) and in response, the memory refresh scheduler changes its policy for issuing refresh commands.