发明名称 CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS
摘要 <p>In various embodiments, an integrated circuit is disclosed. In one embodiments, the integrated circuit comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non- opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.</p>
申请公布号 WO2014066402(A1) 申请公布日期 2014.05.01
申请号 WO2013US66202 申请日期 2013.10.22
申请人 LILJA, KLAS, OLOF 发明人 LILJA, KLAS, OLOF
分类号 H01L27/02;G01R31/3181;G06F17/50;G11C7/24;G11C11/412;H01L27/088;H01L27/092;H03K3/037;H03K3/356;H03K5/1252;H03K19/007;H03K19/0948;H03K19/20;H03K21/10 主分类号 H01L27/02
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