| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a processing system which provides memory attributes without increasing the number of bits required in TLB entries.SOLUTION: A processing system 100 includes a memory configured to store data in a plurality of pages, a TLB 110, and a memory cache 125 including a plurality of cache lines. Each page in the memory includes a plurality of lines of memory. The memory cache is configured to permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache is configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each of the cache lines a page attribute of the line of data stored in the cache line.</p> |
