发明名称 Hardware Architecture and Implementation of Low Power Layered Multi-Level LDPC Decoder
摘要 A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.
申请公布号 US2014122979(A1) 申请公布日期 2014.05.01
申请号 US201213664071 申请日期 2012.10.30
申请人 LSI CORPORATION 发明人 CHEN LEI;YEN JOHNSON;LI ZONGWANG;WANG CHUNG-LI
分类号 H03M13/13 主分类号 H03M13/13
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