A differential MOS capacitor structure includes two capacitor sections coupled to different gates and operating using different signals. The respective signals may be 180° out of phase. The capacitor sections of the differential capacitor each include two or more upper capacitor plates disposed over a single common lower capacitor plate which serves as a common node thereby preventing parasitic capacitance. The upper capacitor plates of a first capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates of a second capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates are formed of a plurality of stacked conductive layers in some embodiments.
