| 摘要 |
The PLL includes a voltage-controlled oscillator (VCO), a frequency down conversion circuit, a phase-frequency detector (PFD), and an adjusting circuit. The VCO is configured to generate an output dock signal. The frequency down conversion circuit is configured to receive the output dock signal and an auxiliary clock signal, and to mix the output clock signal and the auxiliary clock signal to generate a feedback clock signal. By detecting the strength of the feedback clock signal, it provides an auxiliary signal to adjust the frequency of the output clock signal. The PFD is configured to compare the frequencies and the phases of the feedback clock signal and a reference clock signal to generate an adjusting signal. The adjusting circuit is configured to receive the adjusting signal, and to adjust the frequency of the output clock signal generated by the VCO according to the adjusting signal. |
