发明名称 MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE
摘要 Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
申请公布号 EP2344956(B1) 申请公布日期 2014.04.30
申请号 EP20090824176 申请日期 2009.10.30
申请人 MICRON TECHNOLOGY, INC. 发明人 JEDDELOH, JOE M.;LABERGE, PAUL A.
分类号 G06F12/14;G06F12/16;G06F13/16;G06F13/40 主分类号 G06F12/14
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