| 摘要 |
<p>A floating gate memory cell comprises two source/drain regions on a substrate joined by a channel over which are, sequentially, a tunnel dielectric, a floating gate region, a control gate dielectric and a control gate. The tunnel dielectric is so directed that a write tunnel energy barrier is produced when writing data by which tunneling of charge carriers into the floating gate region is enabled. On erasing data an erase energy barrier is formed and the control gate so directed that the erase energy barrier is lower than the writing energy barrier. An independent claim is also included for a production process for the above.</p> |
