摘要 |
<p>According to an exemplary embodiment, a processor such as a digital signal processor (DSP) is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.</p> |
申请人 |
ANALOG DEVICES TECHNOLOGY |
发明人 |
HIGHAM, ANDREW J.;LERNER, BORIS;SANGHAI, KAUSHAL;PERKINS, MICHAEL;REDFORD, JOHN L.;ALLEN, MICHAEL S. |