发明名称 |
Instructions to mark beginning and end of non transactional code region requiring write back to persistent storage |
摘要 |
A processor in described having an interface to non volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non volatile random access memory as persistence storage. |
申请公布号 |
GB201404562(D0) |
申请公布日期 |
2014.04.30 |
申请号 |
GB20140004562 |
申请日期 |
2014.03.14 |
申请人 |
KATHOLIEKE UNIVERSITEIT LEUVEN;LEUVEN;INTEL CORPORATION |
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