| 摘要 |
1,008,329. Electronic digital computers. K. ZUSE, and G. ZUSE, [trading as ZUSE KOMM-GES.]. Dec. 22, 1961 [Dec. 28, 1960; Feb. 1, 1961], No. 46090/61. Heading G4A. A program controlled computer operates with alternate " call " instructions and " arithmetic " instructions, a " call " instruction being effective during its cycle time to retrieve an " arithmetic " instruction from the memory, the " arithmetic " instruction being executed in the immediately subsequent cycle time, the computer having means, when a series of adjacent arithmetic instructions is to be repeatedly executed, for retrieving the next arithmetic instruction from the memory during the execution of the current arithmetic instruction cycle time. As shown in Fig. 1, a computer has a core store KS, arithmetic unit RW, and three registers for registering instructions; a " call " register c, an " instruction " register b serving mainly for serial-to-parallel conversion, and a " control " register r holding the instruction currently being executed. When the instruction sequencing is with alternate " call " and " arithmetic " instructions (called the " twostep " method), a " call " instruction is stored in the "instruction" register b and in the control register r and is effective in the register r during its cycle time T E , Fig. 2, to read out an " arithmetic " instruction from the memory serially to the " instruction " register b, the " call " instruction being, simultaneously transferred via an add one adder Ad1 to the register c. The arithmetic instruction is transferred in parallel to the register r where it is effective during the subsequent instruction execution period T A , Fig. 2, to read out the operand from the memory KS for processing in the arithmetic unit RW, the incremented call instruction being transferred via gate A2 during this period to the register b to be effective during the next instruction call period. The execution of a long series of adjacent instructions is expedited by the provision of the paths shown in thick lines in Fig. 1 and the gates A3-A5. As shown in Fig. 3, during an arithmetic instruction execution cycle time, in addition to the instruction execution, the address part of the call instruction in the register is transferred via the gate A4 to the register r where it is effective to read out in parallel via gate A5 the next arithmetic instruction to the register b the address part of the call instrument being transferred back after incrementation by unity at Ad2 to the call register c. Embodiments employing a drum memory as well as a core memory and having two-address instructions are described with reference to Figs. 5 and 6-8 (not shown). |
