发明名称 |
Processor architecture and method for simplifying programmable single instruction, multiple data within a register |
摘要 |
The present disclosure provides a processor, and associated method, for performing parallel processing within a register. An exemplary processor may include a processing element having a compute unit and a register file. The register file includes a register that is divisible into lanes for parallel processing. The processor may further include a mask register and a predicate register. The mask register and the predicate register respective include a number of mask bits and predicate bits equal to a maximum number of divisible lanes of the register. A state of the mask bits and predicate bits is set to respectively achieve enabling/disabling of the lanes from executing an instruction and conditional performance of an operation defined by the instruction. Further, the processor is operable to perform a reduction operation across the lanes of the processing element and/or generate an address for each of the lanes of the processing element. |
申请公布号 |
EP2725484(A1) |
申请公布日期 |
2014.04.30 |
申请号 |
EP20130187965 |
申请日期 |
2013.10.09 |
申请人 |
ANALOG DEVICES TECHNOLOGY |
发明人 |
SANGHAI, KAUSHAL;PERKINS, MICHAEL G.;HIGHAM, ANDREW J. |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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