发明名称 |
Multi-bit successive approximation ADC |
摘要 |
<p>Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.
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申请公布号 |
EP2587674(A3) |
申请公布日期 |
2014.04.30 |
申请号 |
EP20120189584 |
申请日期 |
2012.10.23 |
申请人 |
SEMTECH CORPORATION |
发明人 |
NYS, OLIVIER;WONG, ARK-CHEW |
分类号 |
H03M1/14;H03M1/06;H03M1/46 |
主分类号 |
H03M1/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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