| 摘要 |
<p>A heterogeneous processor comprises a first physical core having a first instruction set and a first power consumption level, to execute a thread at a first performance level, and a second physical core having a second instruction set and a second power consumption level, to execute a thread at a second performance level. A virtual-to-physical mapping circuit is coupled to the first and second physical cores. The first physical core is mapped to a system firmware interface via a virtual core, and the second physical core is hidden from the system firmware interface. A single physical core may act as a bootstrap processor. The first physical core may act as the bootstrap processor and this may initialize the second physical core. In another embodiment there is a set of one or more small physical cores and at least one large processor core. Two or more small physical cores are exposed to a system firmware interface and the large physical core is hidden from the system firmware interface.</p> |
