发明名称 |
Memory interconnect network architecture for vector processor |
摘要 |
<p>The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.</p> |
申请公布号 |
EP2725485(A2) |
申请公布日期 |
2014.04.30 |
申请号 |
EP20130188947 |
申请日期 |
2013.10.16 |
申请人 |
ANALOG DEVICES TECHNOLOGY |
发明人 |
LERNER, BORIS;PERKINS, MICHAEL G.;REDFORD, JOHN L. |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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