发明名称 Wafer-level chip scale package
摘要 A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.
申请公布号 US8710664(B2) 申请公布日期 2014.04.29
申请号 US201213361716 申请日期 2012.01.30
申请人 LACAP EFREN M.;NARIANI SUBHASH REWACHAND;NICKEL CHARLES;VOLTERRA SEMICONDUCTOR CORPORATION 发明人 LACAP EFREN M.;NARIANI SUBHASH REWACHAND;NICKEL CHARLES
分类号 H01L21/48;B23K35/00;B23K35/02;H01L21/52;H01L21/60;H01L23/485;H01L23/50;H01L29/40;H05K1/02;H05K3/34 主分类号 H01L21/48
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