发明名称 Memory interface circuit, memory interface method, and electronic device
摘要 A memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit detects a logic level of the data strobe signal, which is driven by the memory, in accordance with the data read command.
申请公布号 US8711643(B2) 申请公布日期 2014.04.29
申请号 US201113300033 申请日期 2011.11.18
申请人 KATO YOSHIHARU;FUJITSU SEMICONDUCTOR LIMITED 发明人 KATO YOSHIHARU
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
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