发明名称 Area reduction for surface mount package chips
摘要 Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
申请公布号 US8710645(B2) 申请公布日期 2014.04.29
申请号 US20100686551 申请日期 2010.01.13
申请人 SHAU JENG-JYE 发明人 SHAU JENG-JYE
分类号 H01L23/48;H01R43/00 主分类号 H01L23/48
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