| 摘要 |
A PLL circuit according to the present invention includes a VCO that outputs an VCO signal having a frequency according to an input voltage, a loop filter that feeds a voltage according to an input current to the VCO, a phase comparator that outputs a phase difference pulse having a width according to a phase difference between a first input signal and a second input signal, a charge pump circuit that receives the phase difference pulse, and inputs the current to the loop filter, and a phase-difference-pulse stop unit that stops the input of the phase difference pulse to the charge pump circuit in a non-input state in which an REF signal (reference frequency signal) is not input. The first input signal is the REF signal itself or a signal obtained by dividing the frequency of the REF signal, and the second input signal is the VCO signal itself or a signal obtained by dividing the frequency of the VCO signal. |
