METHOD FOR MODELING DELAY TIME AND OUTPUT TIME OF GATE

摘要

The present invention relates to a modeling method which estimates delay time and output time of a gate when a body bias voltage is applied. A method of modeling the delay time or the output time of the gate according to the present invention includes a step of selecting a first gate among a plurality of gates; a step of determining the structure of the selected first gate; a step of generating the delay time ratio or the output time ratio of the selected first gate according to the determination result; and a step of calculating the delay time or the output time of a second gate when the body bias voltage is applied based on the delay time or the output time of the second gate among the generated delay time ratio or the output time ratio and the gates. [Reference numerals] (110) First delay time table; (120) Delay time ratio table; (130) Second delay time table