| 摘要 |
A parallel-to-series analog-digital converter comprises m-bit parallel analog-to-digital converter, control unit, selection and storage unit, input bus, difference amplifier (subtractor), digital-to-analog converter, first and second buffer register, output buses of high-order and low-order bits of m-bit parallel analog-to-digital converter. Additionally it comprises a subtractor, analog commutation switch and second bus of digital subtractor with m-bit code combination 00…01. |
