| 摘要 |
973,552. Control of D.C. motors. GLOBE INDUSTRIES Inc. June 28, 1963 [July 5, 1962], No. 25886/63. Heading H2J. [Also in Division G3] The output of a crystal oscillator time base A is fed into divider network B supplying a signal to AND-gate D which provides one input to AND-gate E. The other input to the gate E is derived from power circuit F which receives " on " pulses from gate E to allow substantially constant power to be applied to motor M when below speed. A re-setting network H receives a signal from the power circuit to reset the network B in the event of overspeed, which prevents " on " pulses being applied to the motor when the speed is excessive. Feedback pulses from pick-up coil 120 are supplied to circuit G for disabling the transmission of " on " pulses to the motor. The network A comprises a multi-vibrator circuit employing transistors 12, 20, associated with crystal 14, a square wave output being produced on line 29 with negative spikes at the negative-going portions of the square wave. The frequency is divided by three in one portion of network B, and by four in another portion, and the gate D will not produce an output until both portions produce an output pulse at the same time. The 3:1 divider comprises capacitor 64 which is charged until the voltage thereacross exceeds the reference set by potentiometer 36, whereupon transistor 34 is rendered conductive, and the capacitor is discharged through transistors 34, 58, which are then turned off so that the capacitor is recharged. Resistor 62 prevents the circuit from free-running, the capacitor 64 not discharging until a synchronizing signal is received through resistor 38. The 4: 1 divider is similarly arranged. When the pulses from both parts of the divider B coincide, diodes 70, 72 are reverse biased to switch on transistor 80, whereby capacitor 86 is charged through transistor 84 and a positive-going signal is applied to the anode of rectifier 88. When control rectifier 102 in series with motor M is off, a gate signal is supplied to rectifier 88. During underspeed conditions, the signal from gate D is stored in capacitor 86 so that the motor is energized immediately after the rectifier 102 is turned off. Pick-up coil 120 senses the speed of the motor and supplies pulses to the gate of rectifier 138 associated with transistor 134 and transformer 130 supplying pulses to transistor 114 for turning off the control rectifier 102. During overspeed conditions, an off pulse generated by network G, when the rectifier 102 is off, causes a pulse to be coupled through capacitor 68 and diode 30 to reduce the regulated voltage on line 33, so discharging capacitors 64, 50. Thus, no " on " pulses are transmitted to the gate of rectifier 102, capacitor 96 maintaining the input to gate E for a sufficient length of time so that the pulse from gate D is not held by capacitor 86 during this operation. Specification 930,401 is referred to. |
