| 摘要 |
A 10T NVSRAM cell is provided with a bottom HV NMOS Select transistor in each 3T FString removed from traditional 12T NVSRAM cell. A Recall operation by reading a storedΔVt state of flash transistors into each SRAM cell uses a charge-sensing scheme rather than the current-sensing scheme, with all other key operations unchanged. The Recall operation works under any ramping rate of SRAM's power line voltage and Flash gate signal which can be set higher than only Vt0 or both Vt0 and Vt1. Alternatively, the Store operation can use a current charging scheme from a Fpower line to the paired Q and QB nodes of each SRAM cell through a paired Flash Voltage Follower that storedΔVtp≧1.0V. The Recall operation in this alternative embodiment is to use a 7-step approach with the FN-channel erase, FN-channel program and FN-edge program schemes, including 2-step SRAM amplification. |
