SEMICONDUCTOR MEMORY APPARATUS, PROGRAM METHOD AND SYSTEM

摘要

Disclosed are a semiconductor memory apparatus, a program method and a program system. The semiconductor memory apparatus comprises: a memory cell array including a plurality of resistive memory cells; and a control block configured to control at least one of an initial voltage magnitude and an initial voltage applying time to be variable during an incremental step pulse programming (ISPP) mode for the memory cells based on digital code values reflecting resistance states of the resistive memory cells. Therefore, even in the case of the worst cell, since an incremental step of the ISPP may be minimized, writing time may be reduced, and further, unnecessary current consumption may be reduced. [Reference numerals] (20) Row decoder; (30) Column decoding unit; (32) ADC unit; (34) Column decoder; (40) Reading/writing circuit; (50) Interface; (70) DC generator; (AA) Row address (RA); (BB) Column address (CA)