| 摘要 |
Test circuitry (30) for testing for transition delay defects in inter-die interconnects in a structure comprising at least a first die (Die 1) and a second die (Die 2) electrically connected to one another by means of at least a first inter-die interconnect (interconnect 1), comprises
- an input port for receiving a test data value,
- a data storage element (33) for temporarily storing the test data value,
- at least for the first inter-die interconnect (interconnect 1) to be tested, a further inter-die interconnect (interconnect 2) arranged for being electrically connected (32) to the first inter-die interconnect (interconnect 1) so as to form a feedback loop for transferring the test data value from the data storage element (33) back to the data storage element (33),
- a data conditioner for conditioning the fed back test data value so as to make it distinguishable from the stored test data value,
- a clock pulse generator (36) for generating a delayed clock pulse,
- selection logic for applying the generated delayed clock pulse and the conditioned fed back test data value to the data storage element, and
- readout means for reading out a test data value stored in the data storage element (33). |
