发明名称 |
DSP receiver with high speed low BER ADC |
摘要 |
Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC. |
申请公布号 |
EP2722990(A2) |
申请公布日期 |
2014.04.23 |
申请号 |
EP20130004704 |
申请日期 |
2013.09.27 |
申请人 |
BROADCOM CORPORATION |
发明人 |
ZHANG, BO;NAZEMI, ALI;MOMTAZ, AFSHIN;MAHMOUD, AHMADI;ZHANG, HENG;HASSAN, MAAREFI |
分类号 |
H03M1/14;H03M1/06;H03M1/10;H03M1/18;H03M1/36 |
主分类号 |
H03M1/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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