| 摘要 |
<p>A semiconductor device comprising: a first processor; a second processor; a first delay circuit delaying a signal input into the first processor by a predefined number of cycles and inputting the signal into the second processor; a first compression circuit compressing a signal of n-bit width from the first processor into a signal of m-bit width (m<n) and outputting the signal of m-bit width; a second compression circuit compressing a signal of n-bit width from the second processor into a signal of m-bit width and outputting the signal of m-bit width; a second delay circuit delaying the signal from the first compressor by the predefined number of cycles and outputting the delayed signal; and a coincidence comparison circuit comparing bit-wise the corresponding bits of the signals from the second delay circuit and from the second compression circuit to check whether the corresponding bits coincide with each other or not.</p> |
