发明名称 |
Synthesis of area-efficient subtractor and divider functional blocks |
摘要 |
In one embodiment of the invention, a method of designing an integrated circuit including a subtraction arithmetic function is provided. The method includes generating a netlist of an area-efficient subtractor to subtract a first input vector from a second input vector. A netlist of a plurality of reduced full subtractor cells is generated with each including an exclusive-NOR gate evaluating a shared Boolean expression to generate a sum bit output and a carry bit output. The netlist of the reduced full subtractor cell is replicated for all bits of the area-efficient subtractor but for the least significant bit. One of a plurality of netlists of subtractor cells is selected for the least significant bit of the area-efficient subtractor in response to a flex bit. |
申请公布号 |
US8707225(B1) |
申请公布日期 |
2014.04.22 |
申请号 |
US20060399984 |
申请日期 |
2006.04.07 |
申请人 |
DAS SABYASACHI;CADENCE DESIGN SYSTEMS, INC. |
发明人 |
DAS SABYASACHI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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