A recovered clock (123) is generated by making the phase of a reference clock (122) having the same frequency as the data rate frequency of input data (120) match the phase of the input data (120). The input data (120) is written in a FIFO (101) using the recovered clock (123). For readout from the FIFO (101), the FIFO (101) is caused to output recovered data (121) using the reference clock (122) asynchronous to the recovered clock (123).
