MEMORY ACCESS CONTROL MODULE AND ASSOCIATED METHODS

摘要

First (104) and second (106) data interfaces provide data transfer to and from a plurality of memory banks (109A-109D). The first data interface (104) uses a first bus size (bs1) and a first clock frequency (clk1). The second data interface (106) uses a second bus size (bs2) and a second clock frequency (clk2). The second bus size (bs2) is an integer multiple of the first bus size (bs1). The first clock frequency (clk1) is an integer multiple of the second clock frequency (clk2). A channelizer module (105) segments data from the second data interface (106) into data segments of the first bus size (bsl) and transmits them to addressed ones of the plurality of memory banks (109A-109D) using the first clock frequency (clk1). The channelizer module (105) also receives data in accordance with the first bus size (bs1) and first clock frequency (clk1) from the plurality of memory banks (109A-109D), combines this data into the second bus size (bs2), and transmits the data to the second data interface (106) using the second clock frequency (clk2).