| 摘要 |
A processing unit includes a translation look-aside buffer operable to store a plurality of virtual address translation entries, a prefetch buffer, and logic operable to receive a first virtual address translation associated with a first virtual memory block and a second virtual address translation associated with a second virtual memory block immediately adjacent the first virtual memory block, store the first virtual address translation in the transaction look-aside buffer, and store the second virtual address translation in the prefetch buffer. |
