发明名称 |
SAMPLE-AND-HOLD CIRCUIT AND A/D CONVERSION DEVICE |
摘要 |
The present invention is related to a sample and hold circuit and an A/D converter, and prevents an output saturation for an input voltage over a power supply voltage range in the sample and hold circuit. A first switch which is turned on when an input voltage is to be sampled; a sampling capacitor configured to sample the input voltage input via the first switch when the first switch is turned on, and sample a predetermined reference voltage when the first switch is turned off; an adding/subtracting part configured to perform an addition or a subtraction between the input voltage sampled by the sampling capacitor and the predetermined reference voltage sampled by the sampling capacitor; and a hold part configured to hold and output a voltage obtained by the addition or the subtraction by the adding/subtracting part are provided. |
申请公布号 |
EP2571168(A4) |
申请公布日期 |
2014.04.16 |
申请号 |
EP20100851418 |
申请日期 |
2010.05.14 |
申请人 |
TOYOTA JIDOSHA KABUSHIKI KAISHA |
发明人 |
WATANABE, HIKARU |
分类号 |
H03M1/12;G11C27/02;H03M1/38;H03M1/40;H03M1/44 |
主分类号 |
H03M1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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