发明名称 |
Circuit and method for preventing false lock and delay locked loop using the same |
摘要 |
The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal. |
申请公布号 |
US8698527(B2) |
申请公布日期 |
2014.04.15 |
申请号 |
US201213482948 |
申请日期 |
2012.05.29 |
申请人 |
MOON YONG HWAN;RYU YOUNG SOO;SHIM JAE RYUN;JEONG CHUL SOO;KIM SANG HO;SILICON WORKS CO., LTD. |
发明人 |
MOON YONG HWAN;RYU YOUNG SOO;SHIM JAE RYUN;JEONG CHUL SOO;KIM SANG HO |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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